In some field programmable gate arrays (FPGAs) and systems on a chip (SoCs), multiple memory cell arrays are available to instantiate memory resources to be used in a circuit design as implemented on the FPGA or SoC. Multiple memory cell arrays may be cascaded to implement a RAM of a desired size.
FPGAs and SoCs available from XILINX®, Inc., have memory cell arrays that can be put into a sleep mode in order to save power. A sleep pin on each memory cell array provides a dynamic power gating capability for when the memory cell array is not actively used for an extended period of time. A memory cell array may be put into sleep mode during periods of inactivity. When the memory cell array is to be accessed by a circuit, the memory cell is put into standby mode. In sleep mode, the memory cell array maintains the state of data stored therein, but consumes less power than when the memory cell array is in standby mode. An access request is ignored when presented at a port of the memory cell array while memory cell array is in sleep mode. When in standby mode, the memory cell array processes an access request presented at the port of the memory cell array.
The sleep pins on memory cell arrays provide opportunities for circuit designers to reduce the power consumed by implemented designs. However, designers must know at the time the design is created which memory cell arrays are to be used and when the memory cell arrays are to be used in order to benefit from power savings.